1. Field of the Invention
The present invention relates to a process and a device for mixing digital audio signals from a first number of inputs to a second number of outputs.
2. Discussion of Background Information
Processes and devices similar in general to the type described above are referred to as digital or digitally operating audio mixers. Digitally operating mixers make it possible to split incoming sound signals into a number of different channels or to transmit them all together to arbitrary outputs. The individual sound signals can be changed and combined with other sound signals. In this manner, each signal may be multiplied by a factor in a conventional manner and added to other signals and possibly to also delay the sound signals.
Known digital mixers include devices having inputs connected in pairs or groups to digital signal processors (DSPs) and positioned to easily perform such operations as addition, multiplication, and storage of sound signals. However, these known digital mixers are limited in that the number of inputs that may be routed to one signal processor it determined by the number of suitable interfaces that are provided. As a result, the desired calculating capacity for many channels can no longer be achieved. This is particular important with sound signals because sound signals contain relatively large quantities of data in particular time periods.
The above-noted problems caused by large quantities of data are usually exacerbated due to the fact that a single signal processor is associated with a small number of inputs. Thus, with a given number of inputs and outputs, a particular number of signal processors, which must be connected in cascade fashion, are necessary. The greatest problem arises in adding up sound signals from a large number of inputs orjust from a number of signal processors of this type in a so-called sum bus.
For this reason, embodiments with so-called "TDM buses" or systems with shared memories, i.e., "shared memory" systems, are known as sum buses. A TDM bus is a parallel bus that prepares a time window for data from each input channel so that the signals in the bus arrive serially, i.e., one after another. It is likewise conceivable to use DPRAM memories for this purpose and to connect the processors to each other like a so-called "daisy chain." However, each of these embodiments require technical expenditure and are costly.